The present invention disclosed herein relates to flash memory devices, and more particularly to a flash memory device operable with decoding bit lines.
A flash memory device is generally constructed with an array of cells or memory transistors in a form similar to other memories. In particular, a flash memory has floating gates each of which is interposed between a control gate and a substrate in the structure of the memory transistors (or cells), offering non-volatility to the memory cells. As well known in the art of memory, the control gates of the memory cells arranged in rows are coupled to a series of word lines. The memory cells in each row are accessed by selecting a corresponding one of the word lines. Also, drain regions of memory cells arranged in columns are coupled to a series of bit lines. The memory cells in each column are accessed by selecting corresponding bit lines. The drain regions of the memory cells are connected with a common source line. In several kinds of flash memory devices, a memory cell array is divided into a plurality of sectors, which allows flexibility in programming and erasing operations.
Flash memories are generally differentiated into two types; NAND and NOR. A NAND-type flash memory is formed with a structure of strings in which pluralities of cell transistors are coupled to one bit line in series. In the cell transistor of the NAND flash memory, a data bit is stored or erased using the mechanism of Fowler-Nordheim (F-N) tunneling. A NOR flash memory is formed of pluralities of cell transistors that are coupled to one bit line in parallel. In the NOR flash memory, a data bit is stored using the mechanism of channel hot electron injection and erased in the F-N tunneling mode.
In general, because a NAND flash memory consumes a smaller current than a NOR flash memory it is better suited to high integration density. On the other hand, a NOR flash memory is relatively compatible with high frequency operation.
In programming a NOR flash memory cell, predetermined program voltages (e.g., 10V and 5˜6V) are applied to the control gate and the drain region of the memory cell while the source region is grounded. The voltages applied to the control gate and drain region induce hot electrons. The hot electrons are accumulated in the floating gate, which forces the floating gate to be charged to a negative potential, increasing a threshold voltage of the memory cell. This mechanism of electron transmission is called channel hot electron (CHE) injection.
A flash memory device is erased in units called sectors. Erasing a sector as a whole is accomplished by means of the F-N tunneling mode. According to the F-N tunneling mode, a high negative voltage of about −10V is applied to the control gate and a positive voltage of 6˜9V is applied to the semiconductor substrate. The source and drain regions are maintained in a floating state. With this bias condition, a strong electric field of 6˜7 MV/cm is formed between the control gate and the semiconductor substrate, inducing the F-N tunneling. By the F-N tunneling operation, the negative charges accumulated in the floating gate are released to lower the threshold voltage of the flash memory cell.
The memory cells are read by applying predetermined voltages (e.g., 4.5V and 1V) to the control gate and the drain region while grounding the source region. A current or voltage on a bit line is detected by means of a sense amplifier. If the memory cell is programmed, the threshold voltage is relatively high and its corresponding bit line voltage is relatively low. In this case, the channel region of the memory cell is not conductive, which is referred to as an ‘off cell’. In contrast, if the memory cell is erased, the threshold voltage is relatively low and its corresponding bit line voltage is relatively high. In this case, the channel region of the memory cell is not conductive, which is referred to as an ‘on cell’.
In general, the reading operation of the NOR flash memory device is carried out in a random access mode. The NOR flash memory device is also operable in a burst read mode (or synchronous read mode) that continuously reads data from the memory cells to offer a high-frequency reading operation. In the burst read mode, addresses may be generated in sequence in the memory device. Thus, there is no need for a user to provide all addresses. This function is useful when, at the same time, outputting all data of the memory device or data of memory cells belonging to a specific row is required.
However, since in the burst mode, adjacent bit lines are activated in sequence, coupling effects can easily be generated. These coupling effects can be generated even on global bit lines as well as local bit lines. The coupling effects between the bit lines decreases operating speeds during precharging bit lines and reading data, incurring malfunctions in the NOR flash memory device.